In high density memory systems, a typical non-volatile memory cell may include a metal-oxide semiconductor (MOS) transistor whose threshold voltage may be varied for storing a desired information, e.g., by injecting charges into a floating gate or gate oxide. Accordingly, a current sunk by the memory cell in determining biasing states varies depending on the information stored therein. For example, to store information in a twin-transistor single-bit memory cell there is provided two different threshold voltage values for the cell, with each different threshold voltage value associated with a different logic or bit value.
For example, FIG. 1A shows an exemplary non-volatile memory CMOS thin-oxide multi-time programmable memory (MTPM) cell 10 which may be part of a memory device, or system. As shown, the MTPM cell 10 is a twin-transistor single-bit memory cell including first and second transistors 15A, 15B connected in series between first and second cell terminals 14 and 16 sharing a common source line (SL). The first transistor 15A is shown exhibiting a first threshold voltage (Vt), e.g., its native Vt or initial value, and the second transistor 15B exhibiting an induced second threshold voltage, e.g., a Vt+shift (added) voltage.
The CMOS MTPM bit cell structure 10 shown in FIG. 1A further includes two gate electrodes 20A, 20B respectively of the respective first and second transistors 15A, 15B and which are connected to a common wordline (WL) conductor 50.
The first cell terminal 14 may be a drain terminal and the second cell 16 terminal may be a drain terminal—both of which may serve as complementary bitline (BL) terminals (BLs), e.g., BLT (bitline true), BLC (bitline complement), respectively. BLC and BLT can be interchangeable. Other configurations of terminals are known. As further shown, a further source line (SL) is coupled to the connected source of device 15B and source terminal of device 15A. This common transistor terminal 13 is tied to a ground or a 0 volt neutral connection according to the known Grounded Source-Line (GSL) architecture. However, the architecture may be an Elevated Source-Line (ESL) architecture.
A plurality of memory cells may be interconnected by SLs, BLs and gate lines to form a memory array. For example, the two transistors 15A, 15B are designated as “On” cells having a common gate terminal that is held at a high voltage (˜Vdd), however, as shown, other bit cells comprising twin-transistors for other multi-time programmable bit cells may provided as shown in FIG. 1A. For example, further twin-transistors cell (in an Off state) is shown with a first transistor exhibiting a first threshold voltage, e.g., native Vt or initial Vt, and the second transistor exhibiting a second threshold voltage, e.g., Vt+shift (added) voltage. Similar connections for the off-cell transistors are provided to the BLT and BLC (bitline) conductors however their gates are controlled by a separate wordline control 51. Thus, each cell pair may be separately programmed to have a Vt shift induced in either the True or the Complement transistor of the twin-cell.
As known, a threshold voltage Vt is the minimum gate voltage that is needed to be applied to turn on a transistor. The transistor undergoes a Vt shift when it is programmed. Typical Vt values may be about 0.25V to 0.3V. When the transistor is subjected to a high gate voltage (˜2 to 2.2V), and high drain voltage (˜1.5V-1.8V), with source grounded, for a few milliseconds (i.e. when it is programmed), its Vt gets shifted from its nominal value to a higher value (e.g., ˜0.45 to 0.5V) due to BTI (Bias temperature instability) and HCl (hot carrier injection) effects.
For memory write operations, a write control circuit 25 may control writing to the target memory bit cell 10, e.g., in a memory array. For a write operation, an input digital data signal Din represents a programmable bit value to be written to the target memory cell 10 by controlling application of a WL voltage, a BLT voltage a BLC voltage, and an SL voltage to the cell transistors 15A, 15B. That is, write circuit drivers 25 may be implemented to generate and apply programming voltages for bitline true (BLT) and bitline complement (BLC) conductors for writing a bit voltage value to the cells 15A, 15B. The target cell is accessed, e.g., via a voltage provided on the wordline WL 50 corresponding to a row of the memory cell, and bit cell voltage values are written to the T or C cell by applying appropriate voltages to the BLT and BLC terminals corresponding to a selected column (complementary lines) of the target memory cell 10. For example the target multi-time programmable bit cell programming voltages generated are applied to WL, BLT and BLC, e.g., while grounding the SL source line.
When no WL signal is applied, the MOS transistors 15A, 15B do not conduct, but retain their programmed states. The MOS transistors are configured (programmed) to store a logic state. Combinations of voltages can be applied to the first terminal, second terminal and gate terminals of the memory cell 10 to program, inhibit program, read and erase the logic state stored by the MOS transistors.
FIG. 1B shows a chart 40 explaining different modes of operation of the multi-time programmable memory cell 10 of FIG. 1A including example voltages at the terminals of the cell transistors 15A, 15B that provide cell states including stand-by, write, read and reset.
In the current GSL scheme, the cell could be in four different states. These are: 1) a standby state when respective BLT and BLC terminals 14, 16 are floating with a wordline WL of 0.0 Volts applied to the gates of each transistor in the twin-cell 15B, 15A; 2) a write state, e.g., when the respective BLT terminal 14 is at 1.7 Volts and BLC terminal 16 is at 0.0 Volts with a wordline WL of 2.2 Volts applied to the gates of each transistor 15B, 15A; however, the voltages on BLT and BLC could be swapped to store a different logic value in the cell; 3) a read state when each respective BLT terminal and BLC terminal voltage values are close to about 0.5 volts with a voltage delta between BLT and BLC proportional to the Vt shift in the cell, and a wordline WL of 1.0 Volt (VDD) is applied to the gates of each transistor 15B, 15A in the twin-cell; and 4) an erase state, e.g., when the respective BLT terminal 14 is at 1.7 Volts and BLC terminal 16 is at 0.0 Volts with a wordline WL of −1.0 Volts applied to the gates of each complementary transistor 15B, 15A.
Referring to FIG. 1A, generally, in electronic circuits having such bit memory cells 10, the sense amplifier circuit 30 is provided for obtaining a stored bit value, i.e., perform a memory read operation. Typically, the sense amplifier 30 senses whether the T (true) or C (complement) transistor is programmed (Vt shifted). Such sense amplifier circuit 30 reads a selected bit cell BLT voltage and BLC voltage value at respective BLT terminal 14 and BLC terminal 16 conductors for cells selected by an applied WL voltage and as selected by a respective corresponding column select transistor 22B and 22A to select the corresponding target cell via a corresponding Col_Select (T) select signal 23B and/or Col_Select (C) select signal 23A for complementary signals. The column select signals 23A and 23B are the same for one pair of BLT and BLC conductors. As shown in FIG. 1B, the conventional sense amplifier circuit 30 performs a differential read.
In the read operation, the programmed BLT (or BLC) value is dependent upon the sense circuitry of the sense amplifier and across process/voltage/temperature variations. However, the sense amplifier circuitry 30 needs to detect a small differential voltage, e.g., small shifts in Vt signal in the cell between the true/complement transistors 15A, 15B, that may result from a possible threshold voltage shift, e.g., during a read operation 35 of FIG. 1B. For example, the read states of about 0.5 volts (500 mV) with a small data-dependent differential voltage built between BLT and BLC are shown in FIG. 1B for the sensing of BLT programmed state.
Current sense amplifier solutions are limited in that complex sensing structures are required for sensing small signal levels in the cell. Simpler circuits exist only for large signals in bit cells (e.g., SRAM, DRAM applications where difference between stored values is on the order of a ˜VDD (e.g., a supply rail voltage).
There is no sensing scheme that could be employed in cases where a small differential voltage (resulting from a possible threshold voltage shift) could be sensed.